It is generally known to use a bus system to interconnect several groups of components or units of a larger system. Such a bus system has lines for addresses, lines for data, control lines and timing lines. The power supply lines can also be counted in the bus system. By entering an address in the address lines, a certain group of components or a unit is selected, often even a subassembly or a subunit contained therein, possibly a single memory location in a group of memories. A decision is made with control lines, among others, whether the selected group of components will receive or emit data. The data are then transmitted through the data lines. The time of the process is controlled by control lines, timing lines or a combination thereof.
Some bus systems are known, in which the lines for addresses and the lines for data are identical and addresses and data occupy different places in time.
A reason for this is the desire to keep the number of lines, thereby also the number of connection pins of the groups of components and plugs, and finally also the outside dimensions, small.
A further reason is that it is not always possible to clearly differentiate between address and data. On the one hand, entering the address into a selected group of components may already be enough to trigger a very specific sequence in this group of components, without the need for separate control data. On the other hand data, which were transmitted to another group of components, can be used there to address subgroups of components.
It is also known to separate the addresses into two parts (e.g. higher-value and lower-value bytes), and to successively transmit both parts through the same lines. In the same way it is possible, after the transmission of an address, to transmit an entire data block of a determined length in successive parts through the same lines.